(1) Field of the Invention
The present invention relates to a digital phase locked loop to be used for the data modems, etc., and particularly to a circuit which synchronizes the phase of digital phase locked loop clock to a single frequency signal which is extracted from the received signal at a high speed and has a simplified circuit structure.
(2) Description of the Prior Art
In a high speed data communication system, it is necessary to carry out a timing pull-in sequence for synchronizing a digital phase locked loop to the phases of a received signal in order to get the correct data at the receiver. The digital phase locked loop itself is used in the prior art for such phase synchronization. Generally, the digital phase locked loop synchronizes the phase of the received signal by changing the frequency derived from a high frequency oscillator in the receiver. However, such a phase locked loop circuit requires a comparatively long period for phase synchronization and thus, it is not easy to realize the phase synchronization within a short period of time.
For many years, it has been necessary to curtail the pull-in time for phase synchronization and a method to meet such requirement is proposed in the U.S. Pat. No. 3,962,637. In this method the following process is performed. The phase error .phi. is obtained from the relation, .phi.=1-(1/45.degree.). tan (YQ.sub.1 /YQ.sub.0) by using two adjacent demodulated samples (YQ.sub.0, YQ.sub.1), and synchronization is established by controlling such phase error .phi. by making it zero. However, the method of the prior art has a disadvantage in that the scale of a conversion table which performs conversion between the phase error .phi. and 1-(1/45.degree.). tan .sup.-1 (YQ.sub.1 /YQ.sub.0) is large. This is because the sample values YQ.sub.0 and YQ.sub.1 might be able to take zero as well as finite values, where the range of the ratio of sample values .vertline.YQ.sub.1 /YQ.sub.0 .vertline. can vary from 0 to infinity (.infin.) and as a result the value of tan .sup.-1 .vertline.YQ.sub.1 /YQ.sub.0 .vertline. can vary from 0 to infinity (.infin.), thus a large scale conversion table must be prepared. An attempt to realize a small scale conversion table requires a complicated control system.